The present invention relates to a semiconductor device having a decreased parasitic capacitance formed between the electrodes or the interconnection layers, and a method for fabricating the same.
With larger scale and higher integration of semiconductor devices, a minimum processing dimension of the semiconductor devices almost reaches 0.1 μm, which makes it increasingly difficult to form such minimum patterns by the photolithography techniques. In view of such difficulty of the pattern formation, techniques of fabricating elements by using only simple rectangular patterns without using the conventionally used oblique patterns and patterns of complicated configurations are being studied.
A conventional semiconductor device which can be fabricated by using simple rectangular patterns will be explained with reference to FIG. 68A. FIG. 68A is a plan layout of typical layers, which shows a structure of the conventional semiconductor device.
Rectangular device regions 302 are defined zigzag by a device isolation film on the main surface of the silicon substrate (the regions indicated by the one dot chain lines in FIG. 68A). A plurality of word lines 304 are formed, extended longitudinally as viewed in the drawing over the silicon substrate with the device isolation film formed on. Two word lines 304 are extended in each of the device regions 302. Source/drain diffusion layers are formed in the device regions on both sides of the word lines 304. A sidewall insulation film 306 is formed on the side walls of the word lines 304. Contact plugs 308, 310 are buried in the region between the word lines 304, connected to the source/drain diffusion layers. The contact plugs 308, which are buried in the central parts of the respective device regions 302, are extended in the direction of extension of the word lines 304 and overlapping the device isolation film. The contact plugs 310 buried in both end parts of the respective device regions 302 are formed only in the device regions 302. On the silicon substrate with the word lines 304 and the contact plugs 308, 310 formed on, there are formed bit lines 312, connected to the contact plugs 308 through an insulation film covering the word lines 304 and the contact plugs 308, 310, and capacitors (not shown) connected to the contact plugs 310 through the insulation film.
A semiconductor device thus comprising a DRAM including memory cells each including one transistor and one capacitor, which are formed by using only rectangular patterns is fabricated.
In the conventional semiconductor device shown in FIG. 68A, the bit lines 312, the source/drain diffusion layers are connected to each other via the contact plugs 308, so that the device regions 302, the word lines 304, the bit lines 312, etc. are drawn in simple rectangular patterns. The sidewall insulation film 306 of silicon nitride film or others is formed on the side walls of the word lines 304 so that the contact holes for the contact plugs 308, 310 to be buried in are formed by self-alignment with the word lines 304. Accordingly, the long contact plugs 308 extended in the direction of extension of the word lines 304, and the word lines 304 are capacitively coupled with each other through the sidewall insulation film 306 (shaded in the drawing), with a result of parasitic capacitance increase between the word lines 304 and the bit lines 312.
In forming the contact holes for the storage electrodes by self-alignment with the bit lines 312, the sidewall insulation film 314 of, e.g., silicon nitride film also on the side walls of the bit lines 312, which results in increase the parasitic capacitance between the bit lines 312 and the storage electrodes.
Thus, in the conventional semiconductor device, parasitic capacitance decrease is required, as shown in FIG. 68B, between the word lines 304, between the bit lines 312, between the word line 304 and the bit line 312, between the word line 304 and the plugs 308, 310, and between the bit line 312 and the storage electrode.
In not only memory devices of DRAMs having patterns drawn by using only rectangular patterns, but also other memory devices of DRAMs having other patterns, SRAMs, etc., and other devices, such as logic devices, etc., it is desirable to decrease the parasitic capacitance between the interconnection layers.